1. Field of the Invention
The invention relates generally to electrical and electronic circuit designs and, more particularly, to a chip clock design that accommodates low frequency or testing environments without sacrificing performance for the normal design environments.
2. Description of the Related Art
As transistors reduce in size in the newer metal-oxide-silicon field-effect transistor (MOSFET) technologies, TOX (i.e., thickness of the oxide layer) and threshold voltage have also been reducing. When TOX and threshold voltages reduce, there is an increase in leakage currents. Additionally, during chip manufacturing, the transistors are exposed to testing temperatures and voltages. This exposure causes the leakage currents to increase dramatically. Typically, these tests are performed at low frequencies. Low frequency tests, under extreme leakage conditions, make it very difficult to design dynamic logic circuits, because the dynamic logic circuits must be in the evaluation or testing phase for an extended period of time. To insure that the dynamic circuits do not discharge unintentionally due to the excessive exposure to testing environments, it must be considered how much leakage current the dynamic nodes in the dynamic circuits are exposed to. Conventionally, more keeper devices are used to insure functionality under the extreme test conditions. Using an increased number of keeper devices, however, causes the nominal environment performance to suffer.
Therefore, there is a need for a circuit design that accommodates low frequency or testing environments without sacrificing performance for the normal design environments.